This application claims priority under 35 U.S.C. xc2xa7119 to European Patent Application No. 00201949.5-2207-, filed Jun. 2, 2000, the entire contents of which are incorporated herein by reference.
The invention relates to a method for control of a converter station having a voltage source converter coupled between a direct current link and an alternating current network in a high voltage direct current transmission system, the control system having means for control of active power flow between the direct current link and the alternating current network by influencing the phase displacement between a bus voltage in the alternating current network and a bridge voltage of the voltage source converter, and to a control system for carrying out the method.
For a general description of controls systems for voltage source converters reference is made to Anders Lindberg: PWM and Control of Two and Three Level High Power Voltage Source Converters. Royal Institute of Technology, Department of Electric Power Engineering. Stockholm 1995, in particular pages 1, 77-106, and appendix A.
The block diagrams to be described in the following can be regarded both as signal flow diagrams and block diagrams of control equipment for the transmission system. The functions to be performed by the blocks shown in the block diagrams may in applicable parts be implemented by means of analogue and/or digital technique in hard-wired circuits, but preferably as programs in a microprocessor. It shall also be understood that although the in the figures shown blocks are mentioned as members, filters, devices etc. they are, in particular where their functions are implemented as software for a microprocessor, to be interpreted as means for accomplishing the desired function. Thus, as the case may be, the expression xe2x80x9csignalxe2x80x9d can also be interpreted as a value generated by a computer program and appearing only as such. Only functional descriptions of the blocks are given below as these functions can be implemented in manners known per se by persons skilled in the art.
In order not to weigh the description with for the person skilled in the art obvious distinctions, usually the same designations are used for quantities that appear in the high voltage transmission system and for those measured values and signals/calculated values corresponding to these quantities that are supplied to and processed in the control equipment and control system described below.
Parts that are similar to each other and appear in more than one figure are given the same designation numbers in the various figures.
Connecting lines between sensed values and blocks have occasionally been omitted in order not to unnecessary weigh the figures. However, it is to be understood that the respective variables appearing at the inputs of some blocks are supplied from the sensed values respectively from the blocks where they are generated.
FIG. 1 shows in the form of a schematic single line and block diagram a high voltage direct current transmission system as known in the prior art. A first and a second converter station STN1 and STN2 respectively, are coupled to each other via a direct current link having two pole conductors W1 and W2 respectively. Typically, the pole conductors are cables but they may also at least to a part be in the form of overhead lines. Each converter station has a capacitor equipment, C1 and C2, respectively, coupled between the pole conductors, and comprises a voltage source converter CON1 and CON2, respectively. Each converter comprises two three-phase groups of semiconductor valves in six-pulse bridge connection. The semiconductor valves comprise, in a way known per se, branches of gate turn on/turn off semiconductor elements, for example power transistors of so-called IGBT-type, and diodes in anti-parallel connection with these elements.
Each converter is via a phase inductor PI1 and PI2, respectively, coupled to a respective three-phase alternating current electric power network N1 and N2. Although not shown in the figure, it is well known in the art that the converters may be coupled to the three-phase network via transformers, in which case the phase inductors in some cases may be omitted. Filter equipment F1 and F2, respectively, are coupled in shunt connection at connection points between the phase inductors and the three-phase networks.
The ac-voltage of the alternating current network N1 at the connection point of the filter F1 is designated UL1 and is sensed with a sensing device M1. This voltage is in the following called the bus voltage of the alternating current network N1. The ac-voltage set up by the converter CON1 is designated UV1 and is in the following called the bridge voltage of the converter CON1. The alternating current at the converter CON1 is designated IV1 and is sensed with a measuring device M3. Similarly the ac-voltage at the connection point of the filter F2 is designated UL2 and is sensed with a sensing device M4, and the alternating current at the converter CON2 is designated IV2 and is sensed with a measuring device M6. The ac-voltage at the connection point of the filter F2 is in the following called the bus voltage of the alternating current network N2. The ac-voltage set up by the converter CON2 is designated UV2 and is in the following called the bridge voltage of the converter CON2.
The dc-voltage across the capacitor equipment C1 is designated Ud1 and is sensed with an only symbolically shown sensing device M7. The voltage across the capacitor equipment C2 is designated Ud2 and is sensed with an only symbolically shown sensing device M8.
The first converter station comprises control equipment CTRL1 and the second converter station control equipment CTRL2, usually of similar kind as the control equipment CTRL1.
The converter stations can operate in four different modes, one of dc-voltage control and active power control and one of ac-voltage control and reactive power control. Usually, one of the converter stations, for example the first one, operates under dc-voltage control for voltage control of the direct current link, whereas the second converter station operates under active power control and under ac-voltage or reactive power control. The operation modes are set either manually by an operator, or, under certain conditions, automatically by a not shown sequential control system.
A known embodiment of the control equipment CTRL1 is shown in FIG. 2, and illustrated for the case of operation under dc-voltage control for the purpose of voltage control of the direct current link. It comprises a dc-voltage controller UdREG, an ac-voltage controller UaREG, a selector means SW21, and a converter current control system IREG.
The dc-voltage controller is supplied with an actual value of the sensed dc-voltage Ud1 across the capacitor equipment C1 and a voltage reference value Ud1R thereof and forms in dependence on the deviation of the actual value and the reference value an output signal p1R.
The ac-voltage controller is supplied with an actual value of the sensed bus voltage UL1 and a voltage reference value UL1R thereof and forms in dependence on the deviation of the actual value and the reference value an output signal DUL1.
The output signal DUL1 and a reference value Q1R for the reactive power flow through the converter CON1 are supplied to two different inputs on the selector means SW21.
In dependence on a mode signal MD21 either of the output signal DUL1 and the reference value Q1R is transferred and supplied to the converter current control system IREG in the form of a signal designated q1R.
An embodiment of the control equipment CTRL2 as described in the European Patent Application No. 99112542.8 (to be published) is shown in FIG. 3, and illustrated for the case of operation under active power control and reactive power control.
The control equipment CTRL2 comprises a dc-voltage controller UdREG, a calculating member PCALC, an active power controller PREG, an adder SUM, an ac-voltage controller UaREG, a selector means SW22, and a converter current control system IREG, of the same kind as the converter current control system comprised in control equipment CTRL1.
The dc-voltage controller is supplied with an actual value of the sensed dc-voltage Ud2 across the capacitor equipment C2 and a voltage reference value Ud2R thereof and forms in dependence on the deviation of the actual value and the reference value an output signal p2R.
The ac-voltage controller is supplied with an actual value of the sensed bus voltage UL2 and a voltage reference value UL2R thereof and forms in dependence on the deviation of the actual value and the reference value an output signal DUL2.
The output signal DUL2 and a reference value Q2R for the reactive power flow through the converter CON2 are supplied to two different inputs on the selector means SW22.
In dependence on a mode signal MD22 either the output signal DUL2 or the reference value Q2R, in the case illustrated the reference value Q2R, is transferred and supplied to the converter current control system IREG in the form of a signal designated q2R.
The voltage reference value Ud2R is formed in dependence on a voltage reference value Ud2Rxe2x80x2 and a voltage reference correction signal xcex94UdR, the forming of which will be explained below. The voltage reference, value Ud2Rxe2x80x2 can preferably be chosen equal to the voltage reference value Ud1R for the dc-voltage Ud1 across the capacitor equipment C1 at the first converter station.
The active power controller PREG has as inputs a quantity P2 indicative of the actual value of the active power flow through the second converter station and a reference value P2R thereof, and outputs in dependence of a deviation between these inputs the voltage reference correction signal xcex94UdR. The voltage reference correction signal and the voltage reference value Ud2Rxe2x80x2 are supplied to the adder SUM, which forms the voltage reference value Ud2R as the sum of its inputs.
The active power controller comprises in a conventional way a (not shown) controller member, having for example a proportional/integrating characteristic, thus providing feed-back control of the active power flow through the second converter station by way of adjusting the dc-voltage of the second converter station to a value that results in the desired active power flow through the converter. The quantity P2 indicative of the actual value of the active power flow through the second converter station, is calculated in a calculating member PCALC in dependence on sensed values of the bus voltage UL2 and the alternating current IV2 flowing through the converter.
The output signals p1R and p2R of the dc-voltage controllers of the control equipment CTRL1 and CTRL2, respectively, have the significance of an active power order, and the output signals q1R and q2R of the selector means SW21 and SW22, respectively, have the significance of a reactive power order for the respective converter stations. These output signals are supplied to the converter current control systems IREG of the respective control equipment.
The converter current control system IREG is introduced in the purpose to linearise the control of active and of reactive power.
Preferably, the converter current control system is implemented as software run on a microprocessor and executed as a sampled control system. For practical reasons, that is for facilitating the calculations to be described in more detail below, the converter current control system operates in a conventional way with three phase units (voltages and currents of the alternating current network) converted to and expressed in a rotating two-phase dq-reference plane, arrived at via a transformation to a stationary two-phase xcex1xcex2-reference plane. The three phase units of the alternating current network will then be transformed to direct current quantities that can be processed with per se known control system techniques.
Vector units are in the following illustrated with a dash on top ({overscore (x)}). With the phases of the three-phase alternating current network designated a, b and c, the three-phase system is referred to as the abc-system. In the following text and in the figures the reference plane is, where appropriate, indicated as an upper index (for example {overscore (x)}dq).
The transformation of currents and voltages expressed in the abc-reference plane to the dq-reference plane is treated in detail in appendix A of the above mentioned reference Anders Lindberg: PWM and Control of Two and Three Level High Power Voltage Source Converters, but a brief summary will be given here.
A set of three phase quantities of the three-phase abc-system, for example voltages or currents, generally designated xa, xb, xc respectively, are in the xcex1xcex2-reference plane represented by a space vector {overscore (x)}xcex1xcex2, which is arrived at by a transformation defined as                                           x            _                    αβ                =                                            x              α                        +                          jx              β                                =                                    2              3                        ⁢                          (                                                                    x                    a                                    *                                      ⅇ                    j0                                                  +                                                      x                    b                                    *                                      ⅇ                                          j2π                      /                      3                                                                      +                                                      x                    c                                    *                                      ⅇ                                                                  -                        j2π                                            /                      3                                                                                  )                                                          (        1        )            
With xcfx89 designating the angular frequency of the three-phase alternating current network, and with xa={circumflex over (x)} cos(xcfx89txe2x88x92xcfx86),xb={circumflex over (x)} cos(xcfx89txe2x88x92xcfx86xe2x88x922xcfx80/3),and xc={circumflex over (x)} cos(xcfx89txe2x88x92xcfx86xe2x88x924xcfx80/3), the space vector {overscore (x)}xcex1xcex2 becomes
{overscore (x)}xcex1xcex2={circumflex over (x)}ej(xcfx89txe2x88x92xcfx86)xe2x80x83xe2x80x83(2)
which is a vector having the length {circumflex over (x)} rotating with the angular frequency xcfx89 in the stationary xcex1xcex2-reference plane.
A transformation of the space vector {overscore (x)}xcex1xcex2 to a vector {overscore (x)}dq in the dq-reference plane is formally expressed as
{overscore (x)}dq=xd+jxq={overscore (x)}xcex1xcex2*exe2x88x92j"xgr"xe2x80x83xe2x80x83(3)
The direction of the d-axis is defined as the direction of a vector in the xcex1xcex2-reference plane being the transformation of a symmetrical three-phase quantity with the phase displacement xcfx86=0. With "xgr"=xcfx89t the expressions (2)-(3) result in
{overscore (x)}dq={circumflex over (x)}ej(xcfx89txe2x88x92xcfx86)*exe2x88x92jxcfx89t={circumflex over (x)}exe2x88x92jxcfx86xe2x80x83xe2x80x83(4)
which expression represents a vector that in steady state is stationary in the rotating dq-reference plane, having the phase position xcfx86 related to the direction of the d-axis. Thus the vector {overscore (x)}dq can be seen as direct current quantity.
The basic structure of a converter current control system is illustrated in FIG. 4. For the sake of simplicity, all variables are shown in vector form, but it is understood that the signal processing thereof is performed on the components of the respective vector in ways known per see. As the current control systems are similar for both pieces of control equipment, indices 1 and 2 are, for the sake of simplicity, omitted as indices on the respective variables to be described below.
As explained with reference to FIGS. 2-3, the converter current control system receives a signal pR, generated by a super-ordinated controller for dc-voltage control, and a signal qR, generated by a super-ordinated controller for ac-voltage control and for reactive power control, respectively, and generates and outputs in dependence thereon a train Fp of turn on/turn off orders to the semiconductor valves according to a predetermined pulse width modulation pattern.
The converter current control system comprises a current-order calculating unit 41, a current controller 42, transformation members 43 and 44, a phase locked loop (PLL) member 46, and an adder 47.
The output signals p1R and q1R from the respective super-ordinated controllers are supplied to the current-order calculating unit 41, which in dependence thereon calculates and outputs reference values for the alternating current at the converter. The reference values are expressed in the dq-reference plane as IVRd and IVRd respective, and in the figure shown as a current reference vector {overscore (IV)}Rdq=IVRd+jIVRq. The calculation is performed according to the per se known relations
pR=ULdIVRd+ULqIVRq
qR=ULdIVRqxe2x88x92ULqIVRdxe2x80x83xe2x80x83(5)
wherein the voltages ULd and ULq represent d- and q-components respectively, of the bus voltage UL sensed in the alternating current network and transformed to the dq-reference plane in a manner known per se, for example as described in the above mentioned reference Anders Lindberg: PWM and Control of Two and Three Level High Power Voltage Source Converters, pages 80-84, which are hereby incorporated by reference.
The current reference values IVRd and IVRq may be limited in accordance with specified operating conditions for the transmission system before further processing but such limitation means, which may be implemented in per se known ways, are not treated in this a context.
It is noted that in a dq-reference plane rotating in synchronism with the bus voltage, the q-component of the bus voltage becomes zero. It then follows from expression (5) that the d-component of the current reference value becomes a reference value for active power and the q-component a reference value for reactive power.
The current controller 42 comprises a difference forming member 421 (a circle at the input of the adder symbol indicates that the input signal is added with inverted sign), a control member 422, and an adder 423. The difference forming member 421 is supplied with and forms as its output the difference between the current reference vector {overscore (IV)}Rdq and the actual value of the alternating current IV, sensed in the alternating current network at the converter and transformed to the dq-reference plane as a current vector {overscore (IV)}dq (the transformation not shown in the figure). The mentioned difference is supplied to the control member 422, which has a per se known proportional-integral characteristic.
The output signal of the control member is supplied to the adder 423. This adder is also supplied with the current reference vector {overscore (IV)}Rdq, multiplied in a block 433 with a constant factor KL having the dimension of an impedance and a value determined by data at the converter station, as will be explained in more detail below, and a mean value {overscore (UL)}mdq of the bus voltage UL transformed to the dq-reference plane. The generation of the mean value {overscore (UL)}mdq will be further described below. The output signal of the adder 423, designated {overscore (UV)}Rdq,which is the sum of the signals supplied to it, is, as will be further described below, an alternating voltage reference vector for the bridge voltage of converter in the dq-reference plane.
The current controller 42 thus comprises one branch with a feed back control of the it alternating current at the converter, one branch with a feed forward control in dependence of the reference value of the alternating current at the converter, and one branch with a feed forward of the mean value of the bus voltage UL.
The alternating voltage reference vector {overscore (UV)}Rdq is supplied to a transformation member 43, transforming the vector to the xcex1xcex2-reference plane. The output of the transformation member 43 is supplied to a transformation member 44, transforming its input vector to the abc-reference plane as a vector {overscore (UV)}Rabc. This vector is the bridge voltage reference vector for the converter, having as components voltages reference values for the respective three phases of the alternating current system.
The voltage reference vector {overscore (UV)}Rabc is supplied to a pulse-generating unit 45, which, in a way known per se and according to a predetermined PWM (Pulse Width Modulation) pattern, in dependence thereon generates the train Fp of turn on/turn off orders supplied to the semiconductor valves.
The phase locked loop (PLL) member 46 generates, in a way known per se, in dependence on sensed values of the angular frequency xcfx89 of the alternating current network and of the phase position of the bus voltage UL, transformed to the xcex1xcex2-reference plane, a synchronising signal "xgr". The synchronising signal "xgr" represents the transformation angle fused in the above described transformation between the xcex1xcex2-reference plane and the dq-reference plane according to the expression (3) above, and has the purpose of synchronising the rotating dq-reference plane with the bus voltage abc-system. Thus, the synchronising signal "xgr" is an angle linearly increasing with time with a time rate proportional to the frequency of the alternating current network. At least under steady state conditions, the synchronising signal "xgr" is locked to and in synchronism with the phase position of the bus voltage of the alternating current network. When the synchronising signal is in synchronism with the phase position of the bus voltage also the rotating dq-reference plane is locked to and maintained in synchronism with the three-phase abc-system and in particular with the bus voltage. Under these conditions, also the q-component of the bus voltage becomes zero.
An adder 47 is supplied with the synchronising signal "xgr" and a delay angle xcex94"xgr", and outputs and supplies to the transformation member 43 the sum "xgr"xe2x80x2="xgr"+xcex94"xgr" thereof. The transformation member 43 thus performs the transformation from the dq-reference plane to the xcex1xcex2-reference plane according to the expression (3) above using the transformation angle "xgr"xe2x80x2 and not the transformation angle "xgr" generated by the phase locked loop member 46. The delay angle xcex94"xgr" is added due to stability reasons of the current control system and will be explained in more detail below.
The current control system will now be described into some more detail.
The relationship between the alternating converter current {overscore (IV)}dq, the bridge voltage {overscore (UV)}dq, and the bus voltage {overscore (UL)}dq, can be expressed as                                           UV            _                    dq                =                                            UL              _                        dq                    -                      jω            ⁢                          xe2x80x83                        ⁢            L            ⁢                          xe2x80x83                        ⁢                                          IV                _                            dq                                -                      L            ⁢                          ⅆ                              ⅆ                t                                      ⁢                          (                                                IV                  _                                dq                            )                                                          (        6        )            
where L is the phase inductance between the two locations in the network where the two voltages appear, in the transmission system described the inductance of the phase inductor PI1 respectively the phase inductor PI2. The resistance of the circuit is neglected, an approximation that is usually valid in high power circuits.
The current control system is implemented as a sampled control system with a sample period Ts, and a per see known control law giving a dead-beat control of the converter current will now be described. The control law is obtained by integration of the expression (6) and will according to the dead-beat condition give the principal result that {overscore (IV)}(k+1)={overscore (IV)}R(k), that is, the actual current value is equal to its reference value one sample period earlier.
Integration of the expression (6) over one sample period yields the result                                                         UV              _                        R            dq                    ⁡                      (            k            )                          =                                                            UL                _                            m              dq                        ⁡                          (              k              )                                -                      jω            ⁢                          xe2x80x83                        ⁢            L            ⁢                          xe2x80x83                        ⁢                                                            IV                  _                                m                dq                            ⁡                              (                k                )                                              -                                    L              Ts                        ⁡                          [                                                (                                                                                    IV                        _                                            R                      dq                                        ⁡                                          (                      k                      )                                                        "AutoRightMatch"                                -                                                                            IV                      _                                        dq                                    ⁡                                      (                    k                    )                                                              ]                                                          (        7        )            
where the lower index xe2x80x9cmxe2x80x9d indicates the mean value over the sample period.
It can be demonstrated that in taking into consideration low pass filtered values of the positive and the negative sequence components, designated {overscore (UL)}p,fdqand {overscore (UL)}n,fdqrespectively, of the bus voltage, a predicted mean value of the bus voltage during the sample period can be calculated as
{overscore (UL)}mdq(k)={overscore (UL)}p,fdq(k)+{overscore (UL)}n,fdq(k)exe2x88x92j2xcfx89Ts/:xe2x80x83xe2x80x83(8)
where
{overscore (UL)}n,fdq={overscore (UL)}n,fdxe2x80x2qxe2x80x2exe2x88x92j2"xgr"xe2x80x83xe2x80x83(9)
Here the dxe2x80x2qxe2x80x2-reference plane is a plane rotating clockwise in relation to the dq-reference plane making the negative sequence component of the bus voltage stationary in the dxe2x80x2qxe2x80x2-plane.
With a dead-beat control of the current, an approximate value of the mean value of the converter current during the sample period is obtained from the expression                                                         IV              _                        m            dq                    ⁡                      (            k            )                          =                              1            2                    ⁡                      [                                                                                IV                    _                                    R                  dq                                ⁡                                  (                  k                  )                                            +                                                                    IV                    _                                    R                  dq                                ⁡                                  (                                      k                    -                    1                                    )                                                      ]                                              (        10        )            
Before applying the reference value of the converter bridge voltage to the PWM pulse-generating unit 45, it has to be transformed back to the xcex1xcex2-reference plane. In this transformation an additional angle equal to xcfx89Ts/2 has to be added to the transformation angle "xgr" to take into consideration the sample-and-hold property of the sampled control system. Thus
{overscore (UV)}Rxcex1xcex2(k)={overscore (UV)}Rdq(k)ej["xgr"(k)=xcfx89Ts/2]xe2x80x83xe2x80x83(11)
The expression (7) above indicates a control law of feed forward character. In order to reduce the converter current deviation to zero in steady state, the feed back control loop is introduced, comprising the control member 422 supplied with the converter current deviation.
The output xcex94{overscore (U)}PIdq of the controller can be written as                               Δ          ⁢                      xe2x80x83                    ⁢                                                    U                _                            PI              dq                        ⁡                          (              k              )                                      =                              1            Ts                    ⁢                                    H              PI                        ⁡                          [                                                (                                                                                    IV                        _                                            R                      dq                                        ⁡                                          (                                              k                        -                        1                                            )                                                        "AutoRightMatch"                                -                                                                            IV                      _                                        dq                                    ⁡                                      (                    k                    )                                                              ]                                                          (        12        )            
were HPI is the transfer function, that is expressing the proportional-integral characteristic, of the controller.
The expression (7) supplemented with the expression (12) thus becomes                                                                                                               UV                    _                                    R                  dq                                ⁡                                  (                  k                  )                                            =                              xe2x80x83                            ⁢                                                                                          UL                      _                                        m                    dq                                    ⁡                                      (                    k                    )                                                  -                                  jω                  ⁢                                      xe2x80x83                                    ⁢                  L                  ⁢                                      xe2x80x83                                    ⁢                                                                                    IV                        _                                            m                      dq                                        ⁡                                          (                      k                      )                                                                      -                                                                                                        xe2x80x83                            ⁢                                                                    L                    Ts                                    ⁡                                      [                                                                                                                        IV                            _                                                    R                          dq                                                ⁡                                                  (                          k                          )                                                                    -                                                                                                    IV                            _                                                    R                          dq                                                ⁡                                                  (                                                      k                            -                            1                                                    )                                                                                      ]                                                  -                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                                                                    U                        _                                            PI                      dq                                        ⁡                                          (                      k                      )                                                                                                                              (        13        )            
and in which expression the relation {overscore (IV)}dq(k)={overscore (IV)}Rdq(kxe2x88x921) is used.
However, with the control system implemented in a digital signal processor one extra sample period will be required to allow for time needed for calculations to be performed, having as consequence that {overscore (IV)}(k+1)={overscore (IV)}R(kxe2x88x921).
In the expression (8), the transformation of the negative sequence component has to be modified due to the extra time delay, and becomes
{overscore (UL)}mdq(kxe2x88x921)={overscore (UL)}p,fdq(kxe2x88x921)+{overscore (UL)}n,fdq(kxe2x88x921)exe2x88x92jxcfx893Ts/2xe2x80x83xe2x80x83(15)
Similarly, the expression (12) has to be modified and becomes                               Δ          ⁢                      xe2x80x83                    ⁢                                                    U                _                            PI              dq                        ⁡                          (                              k                -                1                            )                                      =                              1            Ts                    ⁢                                    H              PI                        ⁡                          [                                                (                                                                                    IV                        _                                            R                      dq                                        ⁡                                          (                                              k                        -                        3                                            )                                                        "AutoRightMatch"                                -                                                                            IV                      _                                        dq                                    ⁡                                      (                                          k                      -                      1                                        )                                                              ]                                                          (        16        )            
Similarly, expression (11) is modified, due to the extra time delay, to
{overscore (UV)}Rxcex1xcex2(k)={overscore (UV)}Rdq(k)ej["xgr"(kxe2x88x921)+xcfx893Ts/2]xe2x80x83xe2x80x83(16)
The significance of expression (16) is that a delay angle xcex94"xgr"=xcfx893Ts/2 has to be added to the transformation angle "xgr" by the phase locked loop member 46 (not shown in FIG. 5) to compensate for the time delays in the converter current control system.
An implementation of the control scheme is illustrated in FIG. 5, where the blocks having an indicated transfer function zxe2x88x921 indicates a delay of one sample period. A comparison with the expression (13) above shows that the adder 423 corresponds to the equal-sign in the expression. A delay member 424, an adder 428, and a multiplying member 429 correspond to the second term of the expression, where expression (12) is used. The delay member 424, a difference forming member 425, and a multiplying member 426 correspond to the third term of the expression.
A comparison with the expression (15) above shows that the delay member 424, a delay member 427, the difference forming member 421, the control member 422, and a multiplying member 432 correspond to this expression and to the fourth term in expression (13). An adder 430 is introduced for the purpose only of adding the second and third terms of expression (13), the feed forward terms of the current reference value, before supplying the sum thereof to the adder 423.
The figure also shows a transformation member 431 for the transformation of the inverter current vector {overscore (IV)}xcex1xcex2 expressed in the xcex1xcex2-reference plane to the dq-reference plane.
Thus, during normal operation of the direct current transmissions system, the voltage of the direct current link is controlled at a desired value by one of the converter stations. However, it has to be taken into account that disturbances may occur in the transmission system that create abnormal voltage conditions at the direct current link. In particular, such disturbances may cause the dc-voltage to rapidly increase to a level that would exceed safe operation limits of various parts of the transmission system, such as for example the valves of the converters. For this reason, the converter stations are equipped with over voltage protection systems that will block or even shut down the station in dependence on an indication that the dc-voltage has reached a too high level. However, a blocking or a shut down of the station will have negative consequences, such as loss of power. A shut down will also require a restart of the converter station, and possibly the whole transmission system, which is a time consuming procedure.
Thus, to avoid an unacceptable frequency of interruptions in the power transmission system, it is common practice to introduce short-circuiting devices, so called chopper circuits, coupled between the pole conductors, to rapidly reduce the voltage of the direct current link when needed. This is illustrated in FIG. 1, where the first converter station has a first chopper circuit CH1, and the second converter station has a second chopper circuit CH2, each coupled between the pole conductors. Each of the chopper circuits comprises a switch and a resistor connected in series with the switch. The switch is symbolically shown as a mechanical contact but is preferably implemented as a fast controllable semiconductor valve, for example having branches of power transistors of similar kind as are used in the converter valves. The switches are closed in dependence on switching orders SC1 and SC2, respectively, generated by voltage comparing devices UCH1 and UCH2, respectively. The voltage comparing devices are supplied with the dc-voltage sensed across the respective capacitor equipment. In response to that voltage reaching a higher limit value, the respective switch is closed and the capacitor equipment discharges its energy through the resistor, thereby reducing the voltage of the direct current link. The voltage comparing devices have a hysteresis characteristic such that when the voltage has reached a lower limit value, that is lower than the higher limit value, the switch is reset to a nonconducting state. Thus, in the case of temporary disturbances, it is possible to maintain the operation of the converter stations within safe operating limits until the disturbance is cleared, without blocking and shut down of the station.
However, chopper circuits as describe above, having components that have to be designed for the full voltage of the transmission system, are costly and require space at the converter stations.
It is an object of the invention to provide a method of the kind described in the introduction, which permits maintenance of the voltage of the direct current link within safe operating limits also at abnormal voltage conditions at the direct current link, which method is simple and satisfactory from a technical and economic point of view, and a control system for carrying out the method.
According to the invention, this is achieved by the control system comprising detection means for generation of a phase change order signal in response to an indication of an abnormal voltage condition at the direct current link, and means for influencing the phase position of the bridge voltage in dependence on said phase change order signal so as to ensure that the phase displacement between the bridge voltage and the bus voltage will result in an active power flow from the direct current link to the alternating current network.
According to an advantageous development of the invention, said means for influencing the phase position of the bridge voltage comprises means for adding a fixed phase contribution to the phase position of the bridge voltage.
According to another advantageous development of the invention, said detection means comprises means for receiving a sensed value of the voltage of the direct current link, and means for generating said phase change order signal when the amplitude of said sensed value exceeds a first limit value and the rate of change with respect to time of said sensed value exceeds a second limit value.
According to another advantageous development of the invention, the control system further comprises detection means for generation of the phase change order signal in response to an indication that the bridge voltage has lost its synchronism with the bus voltage.
According to another advantageous development of the invention, said detection means comprises means for receiving a reference value for the active power component of the alternating current at the converter and a sensed value representative of the active power component of the alternating current at the converter, and means for generating said phase change order signal when a difference of said sensed value representative of the active power component of the alternating current at the converter and the reference value exceeds a third limit value.
Further advantageous developments and embodiments of the invention will become clear from the following description and from the claims attached thereto.
With the invention, the voltage at the direct current link can be maintained within safe operating limits also at abnormal voltage conditions at the direct current link, without the use of a chopper circuit for this purpose.